The present invention relates to electrical measurements and, in particular, to source measure units.
The use of source measure units (SMUs) has become common in many fields, particularly in the testing of semiconductors, integrated circuits and electronic devices.
Referring to FIG. 1, a basic prior art SMU circuit 10 is illustrated. In understanding these circuits it is important to note that the op-amps will do everything in their power to force the difference between their inputs to zero. If S1 is closed, a voltage corresponding to VDAC will be forced across RLOAD. If S2 is closed, a current corresponding to IDAC will be forced through RLOAD (i.e., VRSENSE/RSENSE is the current through RSENSE and hence through RLOAD). The unforced parameter, current or voltage with respect to RLOAD, can then be measured with unshown measuring equipment.
The current sense resistor is directly in series with the output. Any instantaneous load change will result in a transient across RSENSE (and thus VOUT). Likewise, any instantaneous change in RSENSE (for example, because of a measurement range change) will also result in a glitch on the output. This necessitates “slow switching” of the range elements, adding many components and complicating the range change algorithm, leading to long range change times. RSENSE will also directly interact with capacitive loads forming a pole at 1/(2ΠRSENSE CLOAD). This requires a compensating capacitor across RSENSE, resulting in a settling time of the current sense element when measuring current, and an overshoot of current when sourcing current. A final nuance is that the voltage sense sits on top of the current sensing resistor. Thus RSENSE*IOUT is a common mode term that invariably ends up on the specification sheet as an error in VSOURCE and VMEASURE. 